In order to protect integrated circuits against the potentially destructive effects of large voltage transients, such as those caused by electrostatic discharge (ESD) events, it has become common practice to provide various forms of transient-triggered ESD protection circuits, such as a power supply clamping circuit diagrammatically shown at 10 in FIG. 1. As shown therein a (CMOS, bipolar or BiMOS) integrated circuit 11 is powered by respective (Vdd and Vss) power supply terminals/rails 12 and 14. In addition to coupling reverse-connected protection diodes D1/D2 and D3/D4 between respective signal input and output pins/ports 21 and 23 and the supply rails, a voltage transient (dv/dt)-responsive clamp circuit 40, typical bipolar and MOS-configured examples of which are shown schematically in FIGS. 2 and 3, respectively, is coupled across the supply rails.
Each clamp circuit has first and second ports 41 and 42, coupled to the respective power supply terminals Vdd, Vss. Ports 41 and 42 are bridged by a resistor R1--capacitor C1 network 43, having a sense/control node 45 as a control input to the clamp circuit 40, shown as a Darlington-connected bipolar transistor pair Q1-Q2 in FIG. 2, and a CMOS inverter (Q1-Q2) driven output MOS device Q3 in FIG. 3.
In operation, a portion of a sensed ESD pulse is coupled via the discharged input capacitor C1 and resistor R1 to the sense node 45 and is used to turn on the switched components of the clamp circuit 40, so as to clamp the voltage applied across the circuit at a preset, tolerable value. Eventually, the capacitor C1 is charged to the voltage across ports 41 and 42, turning off the clamp circuit 40, and returning the circuit to its previous (inactive) state.
The values of the resistor--capacitor network 43 (i.e. its RC time constant) and the switching characteristics of the clamp circuit control how long the clamp circuit will conduct. This RC time constant is typically set at a value that is close to or slightly longer that of the ESD waveform (e.g., on the order of 150 ns for the standard human body model (HBM)), to ensure that the protection circuit will be active for a duration sufficient to discharge the entire ESD pulse. However, too long an RC time constant can present problems, if rapid voltage transitions occur across the clamp circuit during normal operation.
For example, if the part containing the integrated circuit 10 and its associated clamp circuit is connected across powered positive and negative supply rails (a `hot` insertion), the clamp circuit may be subjected to a very rapid voltage transition. Such a rapid voltage transient may also be caused by inductive voltage drops across the part's bondwires and lead frame during rapid current transitions. If the peak of the rapid voltage transient is high enough, it may turn on the protection circuit, which is undesirable during normal operation (although it may not be catastrophic, if the clamping circuit conducts for only a relatively abbreviated period of time, as governed by the RC time constant).
A further shortcoming of conventional overvoltage clamp circuits is their sensitivity to noise in the vicinity of their triggering threshold. Moreover, because these circuits have the potential to oscillate during an ESD transient event, they can take longer than necessary to discharge an ESD pulse. Such unwanted oscillation may occur, if the clamp circuit locally reduces the voltage on the supply rails fast enough to capacitively couple to the control node and reduce its voltage below the clamp threshold. The clamp circuit would then turn off; if the ESD pulse had not been fully discharged, however, the voltage at the supply terminals would begin to rise. This voltage increase would, in turn, couple to the control node and turn the clamp circuit back on--a cycle that could be repeated several times (oscillation).